Samsung to build Nvidia's NVHBM base dies on TSMC's 3nm process, report says

What the Seoul Economic Daily reported

Samsung Electronics will use TSMC's 3-nanometre manufacturing process to make the base die for Nvidia's custom high-bandwidth memory, the Seoul Economic Daily reported on 18 October 2026, citing industry sources. According to the paper, Nvidia asked all three of its suppliers for the product, Samsung, SK hynix and Micron, to build the NVHBM base die on TSMC's 3nm process and to standardise the stacked memory dies on the sixth-generation DRAM process known as 1c.

The paper says Samsung's Device Solutions division accepted the request after an internal review. If accurate, it would be the first time Samsung has worked with TSMC at the HBM manufacturing stage. The two companies cooperated about four years ago on compatibility with TSMC's packaging process, but they compete directly in contract chipmaking. Reuters relayed the report the same day; neither Reuters nor the paper quoted Nvidia, Samsung or TSMC confirming it, and we found no public statement from any of the three by the evening of 18 October.

Samsung is not abandoning its usual approach entirely. The paper says it will keep making both layers of the stack itself, the so-called turnkey model, for standard HBM and for custom memory built for other customers including AMD. It also says Samsung is testing whether its own foundry could make NVHBM base dies as a hedge in case demand outruns TSMC's capacity.

What NVHBM is

Nvidia announced NVHBM on 26 August as part of NVLink Fusion, the programme that lets cloud companies connect their own custom accelerators to Nvidia's rack-scale systems. HBM is the stacked DRAM that sits beside an AI chip on the same package. At the bottom of each stack is a base die, a logic chip that connects the memory layers above it to the processor. In standard designs the memory controller lives on the processor. NVHBM moves Nvidia's custom memory controller into the base die.

Nvidia says that change delivers up to 30% more memory bandwidth and 15% lower HBM power than standard HBM4E. The company's technical blog adds that a narrower custom physical interface cuts the area needed for the memory interface by up to 67% compared with the JEDEC HBM4E standard. Nvidia gives the resulting gain in compute area as up to 25% in its announcement and up to 30% in the technical post. All of these are Nvidia's own figures; no independent measurements have been published.

Nvidia also says it is establishing one standard NVHBM implementation that several memory makers will offer, so that chip designers do not have to qualify a different memory design from each supplier. Amazon's Annapurna Labs is the first named partner and plans to support NVLink Fusion starting with its Trainium4 chips. The Seoul report is essentially about how that standard design gets manufactured.

Why Nvidia wants the base die on TSMC's 3nm

A second Seoul Economic Daily article explains the reasoning as the paper understands it. Putting the memory controller and other functions from the GPU onto the base die requires packing more circuitry into a small area, which calls for a very advanced logic process. Making those chips cheaply also depends on high yields, the share of working chips on each wafer.

The paper cites industry estimates that TSMC's 3nm yield is above 90%, compared with roughly 60% for Samsung Foundry's comparable 2nm SF2 process. Those are unofficial estimates rather than figures either company has published, but they help explain why Nvidia would prefer a single foundry for a part that every NVHBM stack needs, regardless of which memory maker supplies it.

The other reason is consistency. Each memory maker currently builds its base die its own way. Samsung uses its own 4nm process for the base die of HBM4 and HBM4E, the paper says, while SK hynix and Micron have their own arrangements. Standardising on one process gives Nvidia one design to validate instead of three, which is the stated purpose of NVHBM.

Capacity is the other bottleneck

The Seoul Economic Daily frames the deal as much about supply as about technology. It cites a UBS projection that HBM demand next year will reach about 61.5 billion gigabits, up 91% from this year, while new shipments from memory makers will reach only about 54.6 billion gigabits, leaving a shortfall of around 10%.

According to the paper, Samsung makes its HBM core dies on 1c DRAM lines at its Hwaseong and Pyeongtaek campuses, but its 4nm base-die capacity is limited to one line at Hwaseong and part of one plant at Pyeongtaek. That set-up was built around existing HBM demand and would struggle to absorb custom volumes such as NVHBM on top of its own products.

TSMC, by the paper's account, has room to grow. It says TSMC told investors at its third-quarter results that it will add two 3nm lines at Fab 18 in Tainan, with mass production starting in the first half of next year and the first half of the year after, and plans 3nm lines at its second Arizona plant and its second plant in Kumamoto, Japan. An industry official quoted by the paper warned that TSMC's 3nm lines also serve high-performance computing and smartphone chips, so allocations could hit a ceiling, which is why Samsung is validating NVHBM base dies on its own 2nm process.

What it means for chip buyers

For companies building their own AI accelerators, the appeal of NVHBM is less engineering work per supplier and more silicon left for compute. That matters in a market where hyperscalers are designing chips such as Microsoft's Maia 300 and Amazon's Trainium line, and where memory capacity and bandwidth are often the limiting factor, as Intel's choice of 480 GB of LPDDR5X for its Crescent Island inference GPU shows.

The arrangement also shifts more of the memory stack's design toward the chip designer. Nvidia sets the controller and interface, TSMC makes the logic layer, and the memory makers supply the DRAM and assemble the stack. It fits Nvidia's broader push to define more of the data centre around its own standards, from NVLink Fusion to the Vera Rubin rack specifications it has brought to the Open Compute Project.

For Samsung, the report describes a pragmatic concession: giving up part of its turnkey model for one important customer while keeping it for everyone else. For TSMC, it would mean a bigger role in a component that memory makers have traditionally built themselves.

What has not been confirmed

The core claims rest on unnamed industry sources quoted by one Korean newspaper and relayed by Reuters. The articles do not give production volumes, start dates, prices or the share of NVHBM base dies that will come from TSMC versus Samsung's own fabs. They do not say whether SK hynix and Micron have formally agreed to the same terms.

The performance numbers attached to NVHBM are Nvidia's projections against standard HBM4E, published before any product shipped. Until Nvidia, Samsung or TSMC comments, or the arrangement shows up in earnings calls or supply announcements, the report is best treated as a credible but unconfirmed account of how Nvidia's custom memory will be built.