NVIDIA opens Vera Rubin rack designs at OCP and plans USFP optics with Cisco

What did NVIDIA announce at the OCP Global Summit?

NVIDIA used the OCP Global Summit, held at the San Jose McEnery Convention Center, to bundle several infrastructure announcements under one theme: open standards for what it calls AI factories. Ian Buck, NVIDIA’s vice president of hyperscale and high-performance computing, spoke at the summit about open infrastructure, and NVIDIA’s blog post went live on 12 October at 18:00 Athens time.

The package has six parts. NVIDIA contributed its Vera Rubin rack and compute-tray designs to the Open Compute Project, the industry group that publishes open data center hardware designs, as part of an updated MGX 1.2 specification. It published a separate design specification for a Vera CPU rack aimed at agent workloads. It released four open-source components for DSX OS, its software layer for running AI factories. It co-authored two facility standards with hyperscalers. Meta said it is building switches on NVIDIA’s Spectrum-6 silicon, and Google’s Falcon transport protocol will run on future NVIDIA network cards.

The sixth part came in a joint press release with Cisco: a new pluggable optical module format called USFP. Most of the package is specification work and roadmap. Very little of it is hardware a buyer can order today, and NVIDIA did not give prices or ship dates for any of it.

What is in MGX 1.2 and the Vera Rubin contribution?

MGX is NVIDIA’s modular reference architecture for servers and racks. The third generation was developed through OCP’s Open Data Center initiative, and version 1.2 is the version written around Vera Rubin, NVIDIA’s next rack-scale platform after Grace Blackwell.

According to NVIDIA, MGX 1.2 adds rack-scale blind-mate liquid cooling, where trays connect to coolant lines automatically as they slide in, an interoperable rack-scale interconnect, and a liquid-cooled 5,000-amp busbar for higher-power systems. It adds native support for standard 19-inch equipment, higher-density rack layouts, configurable I/O bays, fanless liquid-cooled compute trays and standardised power and cooling interfaces. NVIDIA says the architecture supports rack deployments of up to 250 kW. It pairs the spec with open liquid-cooling connector designs known as MQD and MQDB.

Joe DeLaere, NVIDIA’s product lead for AI infrastructure solutions, framed the reason in a press briefing reported by SDxCentral: “The bottleneck for AI factory buildouts is how fast we can manufacture and deploy.” With an open specification, he said, equipment makers can start fabricating right away “instead of waiting for a singular customer with one proprietary spec.”

That is a real benefit for suppliers of racks, manifolds, busbars and cold plates, who can design to one public target. It is also good for NVIDIA. The open parts are the mechanical, power and cooling layers around the GPUs, and the compute trays in those racks still carry NVIDIA silicon.

Why publish a separate Vera CPU rack for agents?

The second rack spec extends MGX beyond GPUs. NVIDIA describes the Vera CPU rack as a platform “designed to support tool calling, orchestration and sandboxed execution, helping AI agents interact with applications, data and services in real time,” while Vera Rubin NVL72 handles large-scale training and inference. SDxCentral reports that NVIDIA said the Vera CPU rack has started shipping.

The argument mirrors the one AMD made the same day. AMD’s Helion blueprint is an OCP rack design that runs agents on EPYC CPUs, either CPU-only or alongside a small number of GPUs. Both companies are betting that agents spend much of their time on CPU work, such as running code, calling tools and moving data between model calls, and that this work needs its own rack-scale capacity.

The difference is in who owns the stack. AMD sells both server CPUs and GPUs and pitches Helion as a CPU-first design. NVIDIA’s Vera CPU rack sits on the same MGX architecture as its GPU racks, so a buyer who standardises on MGX gets a consistent mechanical, power and cooling design for both. NVIDIA has not published core counts, power figures or benchmark results for the Vera CPU rack in the summit material.

What do the Open Data Center and grid resilience specs set?

The facility work is the most concrete part of the package. The Open Data Center Specification, revision 0.7, lists AMD, Google, Meta and NVIDIA as authors and sets design principles for AI data halls built in 2027 and 2028. Google wrote the first draft in December 2025; version 0.7 broadened it to the four companies and removed Google-specific tables.

The numbers are specific. The heaviest single rack is targeted at 8,000 lb (3,629 kg) on a 28-by-48-inch footprint, and a rack plus its power sidecar can reach 15,000 lb. Racks are 100 inches tall and 71 inches deep. Halls need an 18-foot minimum ceiling for two-busway rows. Instead of fixed row lengths, the spec uses power per foot of row: a blended average of 25 kW per foot, a peak of 125 kW per foot expected in 2027 and 350 kW per foot for the densest machine-learning racks. Cluster size starts at 12 MW, with 24 MW preferred.

At 350 kW per foot, the spec expects liquid cooling to carry 335 kW per foot and air the remaining 15. That is a different building from the air-cooled halls most enterprise data centers still run.

The second standard, the OCP Grid Resilience Specification from Google, Meta, Microsoft and NVIDIA, covers how AI campuses behave when the utility grid wobbles: stay connected, respond automatically and restore near-full load in under two seconds. NVIDIA also highlighted Visionbay’s planned K-1 AI factory, which combines NVIDIA’s 800 VDC power architecture with Vertiv power and thermal equipment and is designed to phase in direct-current distribution rather than switch over at once.

What is USFP, and why does it matter for AI networks?

USFP stands for Ultra-Dense Small Form Factor Pluggable. In their joint announcement, NVIDIA and Cisco call it the first module designed for 400 Gb/s-per-lane electrical signals. The first planned transceivers fit 16 full-duplex lanes into roughly the footprint of today’s OSFP modules, with a path to 32 lanes, for up to 12.8 Tb/s of capacity. As our guide to AI chip metrics notes, moving data between chips is often as limiting as raw compute.

Against 200 Gb/s-per-lane pluggables, the companies claim four times the bandwidth and front-panel density and about 1.3 times the power efficiency. The point is to connect more 1.6 Tb/s endpoints per switch so that large clusters need fewer switch tiers, which saves optics, power and latency. The modules use a new two-dimensional connector with two-step insertion to reduce contact wear and can dissipate up to 100 W without a dedicated cooling circuit inside the transceiver.

TE Connectivity and Amphenol are building cages, connectors and modules, and NVIDIA and Cisco plan an open multi-source agreement through a community-led project.

Cisco’s Bill Gartner said scaling pluggables to 400 Gb/s per lane “would require more than another incremental extension of today’s module designs.” Cisco’s own blog post adds a caveat worth keeping: the industry is still working on near-packaged and co-packaged optics too, and customers will choose among them.

What are Meta and Google adopting?

Meta is adopting NVIDIA Spectrum-6 Ethernet switches, rated at 102.4 Tb/s, for future Vera Rubin clusters. Its new N-IceCube switch slots into IcePack, Meta’s liquid-cooled 102.4T network rack, and runs FBOSS, Meta’s open-source switch operating system, on top of the OCP Switch Abstraction Interface.

The deal rests on Spectrum-X Multiplane, which spreads GPU traffic across up to eight independent network planes so clusters can pass 100,000 GPUs with fewer switch tiers and keep running at reduced bandwidth if a plane fails. “Extending FBOSS to Spectrum ASICs means we can run that same software stack across our fabrics,” said Omar Baldonado, senior director of data center and AI networking at Meta.

Google’s contribution runs the other way: its Falcon transport protocol, which handles multipath load balancing, congestion control and loss recovery over Ethernet, will be supported on future ConnectX-10 SuperNICs and BlueField DPUs.

On software, NVIDIA released a Config Manager for switch fleets, a Cluster Readiness Engine that stress-tests GPU clusters before training starts, a Rack Management Service and a Cluster API provider for bare-metal provisioning. All four are Apache-2.0 repositories on GitHub.

What is still unproven?

The specifications are drafts or first versions. The Open Data Center spec is at revision 0.7, the USFP multi-source agreement does not exist yet, and NVIDIA’s summit material gives no dates for partner hardware built to MGX 1.2. The efficiency figures for USFP are vendor projections for modules that have not shipped.

Openness here has limits. The contributions standardise the physical plant around NVIDIA’s systems, which helps suppliers but also makes NVIDIA’s rack the default target for everyone else. Hyperscalers are building their own chips at the same time, as Microsoft’s Maia 300 shows, and how much of the open facility spec they apply to non-NVIDIA racks will show whether these are industry standards or NVIDIA standards with an OCP logo.

For data center operators, the practical message is about buildings, not chips: plan for floors that hold 8,000-lb racks, for liquid cooling that carries most of the heat, and for power systems that ride through grid disturbances on their own.