Qwenputer puts a working RISC-V CPU inside the weights of Qwen3.5-4B

What Qwenputer does

Startup Fortune reported that developer Divyansh Agrawal built Qwenputer, a 32-bit RISC-V CPU — RV32IM with the Zba extension and a bignum coprocessor — compiled into the weights of Qwen3.5-4B, an open-weight model from Alibaba. The original model weights remain unchanged; 11 extra transformer layers are added in front of Qwen's own, and none of those added layers are trained.A compiler computes every weight in them directly, turning logic gates and instruction decoding into fixed linear algebra the model can run during inference. There is no emulator loop, no interpreter, no Python script stepping through instructions: the forward pass of the model is the CPU executing.

The mechanics

The model's existing Gated DeltaNet layers get repurposed as RAM — Gated DeltaNet being a linear-attention mechanism Qwen uses for long-context efficiency. When a program executes, its memory state is literally stored in the hidden state of a language model reading tokens.

The chip is not a toy simulation that approximates RISC-V behavior: according to the project's documentation it passes the riscv-tests instruction tests and its programs match QEMU. It also runs C and MicroPython code within the model's forward passes.

The benchmark gap

Agrawal tested the setup on NUPA, a benchmark built by researchers at Peking University that isolates basic numerical operations — arithmetic, comparisons, digit understanding and format conversion — from broader reasoning skills. The Qwenputer configuration scored 100% on NUPA against 48.6% for the unmodified Qwen3.5-4B base model.

The gap is the whole point of the project. A small model doing arithmetic by 'thinking' about numbers gets it wrong close to half the time. The same model executing a deterministic instruction set gets it right every time: at that point it isn't reasoning about the math, it's just running the circuit.

Performance and limits

On an Nvidia L4 GPU running through a Triton executor, the system processes roughly 3,200 trace tokens a second — slow next to actual hardware, but fast enough to boot and run interactive programs. The added layers and wider dimensions make the published checkpoint larger than the base model.

Calling this a product shortcut would be a stretch: a RISC-V core costing a few dollars in silicon is staggeringly faster. Nobody is going to deploy a language model as a replacement for an actual processor. The value is in what the artifact demonstrates.

What it means

As a research artifact, Qwenputer says something sharper than its speed numbers: a system built around a 4-billion-parameter open-weight base model can hold a working general-purpose computer in compiler-generated layers, executing programs through nothing but forward passes. RISC-V is an open instruction set implemented in commercial silicon, so this is a real, general-purpose instruction set — not a fixed toy renderer.

The project points toward interpretability research that treats a model's internals as inspectable hardware, and toward a harder question: how much deterministic computation can be folded into a neural network before the line between 'model' and 'computer' stops meaning much at all. It also adds to a lineage of work using neural networks as programmable machines rather than statistical text predictors.

Caveats and what to watch

The riscv-tests suite is not a complete verification or certification standard, so passing it demonstrates correct execution across the covered instruction tests without being exhaustive certification. The performance figures and benchmark scores come from the developer's own documentation and coverage, not independent replication.

Watch whether the technique generalizes: can non-RISC-V architectures or larger useful programs be folded into other open models' weights with the same compiler approach, and does anyone reproduce the NUPA results independently?

The compilation approach

The key trick is that the added layers are not trained at all: a compiler computes every weight directly, turning logic gates and instruction decoding into fixed linear algebra. That means the CPU's behavior is hard-wired into the weights rather than learned, which is why the model can execute RISC-V instructions correctly instead of approximating them statistically.

Using the model's own Gated DeltaNet layers as RAM is the other half of the design. Gated DeltaNet is a linear-attention mechanism, which means state can be stored in the hidden state and carried through the forward pass — exactly what a CPU needs for registers, memory and a program counter. The result is a model whose hidden state is literally a running computer.

The bigger research direction

Qwenputer joins a line of work probing what neural networks are beyond statistical text predictors. Earlier projects compiled game renderers or fixed functions into weights; Qwenputer targets a general-purpose instruction set that anyone can compile programs for, which is a material step toward models as inspectable, programmable machines.

The interpretability angle matters: if computation can be folded deterministically into layers, then at least some of what a model does is not 'reasoning' in the fuzzy sense but literal execution. Designing tools to detect and isolate such compiled computation inside a model could eventually help researchers understand what pre-trained models are actually doing internally — and spot when emergent behavior is really just an embedded program no one placed there.

Caveats

NUPA tests basic numeracy, not general reasoning, so the 100% figure says nothing about language or reasoning quality — the base model's language abilities remain as they were. The riscv-tests suite covers the tested instruction set but is not full certification.

The execution speed (about 3,200 trace tokens per second on an L4) makes this a research artifact, not a usable CPU. Referencing Qwenputer as any kind of product or chip alternative would misread the project.